1. Field of the Invention
This invention relates to a semiconductor device which has a low ON-resistance, and further, to a method of manufacturing such a semiconductor device.
2. Description of the Related Art
Many kinds of methods of manufacturing for reducing an ON-resistance of a semiconductor device have been known. For example, Japanese Unexamined Patent Publication 1-169970 discloses a method which an N-type impurity layer is formed in a back surface of a drain substrate so as to reduce a contact resistance between the drain substrate and a drain electrode. Japanese Examined Patent Publication 58-45814 discloses a method of manufacturing the semiconductor device which has a good ohmic contact between the drain substrate and the drain electrode. The device has a multilayer metal electrode on a back surface of a drain substrate. The multilayer metal electrode consists of layers having a gold layer as a main layer.
As shown in FIG. 13, the ON-resistance of a field effect transistor (FET) is represented by the following equation:RON=R1+R2+R3+R4+R5+R6+R7+R8+R9+R10wherein, R1 denotes a contact resistance of a drain electrode 50; R2 denotes a contact resistance between the drain electrode 50 and an N-Type impurity layer 52; R3 denotes a resistance of N drain substrate 54; R4, R5 and R6 denote resistances of N drain region 56 respectively; R7 denotes a resistance of P-Type diffusion region 58 for forming a channel; R8 denotes a resistance of N-type source 60; R9 denotes a contact resistance between the N-Type source 60 and a source electrode 62; and R10 denotes a resistance of the source electrode 62.
However, such a conventional method of manufacturing the semiconductor device has many problems. For example, the method by which the N-Type impurity layer is formed is complex because an oxide film adhered to the back surface of the N drain substrate 54 and a diffusion layer having an opposite conductive type (P) to that of the N drain substrate 54 must be removed before the N-type impurity layer 52 is formed.
A semiconductor device for household use is demanded with a withstanding voltage more than 100V, normally more than 200V. It is a necessary to make a resistance of a epitaxial layer (the N drain region 56) formed on the N drain substrate 54 high to get the withstanding voltage. Therefore, the ratio of the resistance of the N drain substrate 54 to the resistance of the epitaxial layer becomes small. On the contrary, a semiconductor device for a motor vehicle is demanded with a withstanding voltage of at most 50-60V. The resistance of the epitaxial layer is relatively low, and the ratio of the resistance of N drain substrate 54 to the resistance of the epitaxial layer becomes large. Therefore, in the semiconductor device for a motor vehicle, it is effective to reduce the resistance of the N drain substrate 54 for reducing the ON-resistance.
The resistance R3 of the N drain substrate 54 is represented by the following equation:R3=ρN×tn/Swherein, ρN denotes resistivity of the N drain substrate. 54; tn denotes a thickness of the N drain substrate 54; and S denotes a cross section of the N drain substrate 54. It is necessary to reduce the thickness tn of the N drain substrate 54 so as to reduce this resistance R3. However, the thickness tn of the N drain substrate 54 for forming the N-Type impurity layer 52 is determined in accordance with a thickness of a silicon wafer. The reason is that the N drain substrate 54 is warped by heat generated in a step that the N-Type impurity layer 52 is formed when the thickness tn of the N drain substrate 54 is too thin. To get a wafer of large diameter, the thickness tn needs to be thick to keep the strength thereof. Therefore, the resistance R3 of the N drain substrate 54 becomes high, and thus the ON-resistance also becomes high.
The technique by which the concentration of antimony (Sb) as a impurity in the N drain substrate 54 is heightened and the resistivity is diminished, may be adopted so as to reduce the resistance R3 of the N drain substrate 54. However, it is impossible to make the resistance R3 less than 0.01 Ω·cm because of the limitation of the amount solution of Sb which can be in the solution.
Moreover, since it is impossible to make the impurity concentration in the substrate high because of the limitation of solution, it is difficult to get a good ohmic contact between an N-type substrate and an electrode.
On the other hand, in the method which utilizes gold as an electrode material, the barrier height of the gold for an P-type silicon substrate is 0.2 eV, and therefore so a good ohmic contact between those can be obtained. However, since the barrier height of the gold for an N-type silicon substrate is relatively high, 0.8 eV, the contact between those becomes a schottky contact and may have undesirable diode character.
Moreover, when an overall thickness is thick, stress from a package and a step between a lead frame and the source electrode 62 becomes higher. Therefore, the wire bonding work becomes very difficult. Also, the cost of gold is very high.
Techniques other than the aforementioned techniques have also been known. The technique which is disclosed in Japanese Unexamined Patent Publication 57-15420 suggests that a back surface of a silicon substrate is ground to improve adherence between the back surface and a collector electrode formed on the back surface. The technique which is disclosed in “IEEE ELECTRON DEVICE LETTERS, VOL. 10, NO. 3 MARCH 1989, P101-103” suggests that a 0.004 Ω·cm arsenic-doped silicon substrate is used.